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Mr. David John, specialist, Tata Elxsi ,previously Design Engineer at Montalvo Systems and Staff CAD engineer at Cypress semiconductors. David John figures in the list of IEEE NDLP speakers and he specializes in VLSI, ASIC design, FPGA design, Embedded systems.

The IEEE NDLP talk will be one day long. The morning session will feature a seminar on EDA tools and the evening session will include a hands-on session. Fedora Electronic Lab includes working on Fedora with extensive hardware design and simulations tools following the industry's current trend. This platform provides different hardware design flows based on the semiconductor industry's current trend. FEL maps in new design, simulation and verification methodologies with opensource EDA software.

Forenoon session

  • Introduction to VLSI - 0.5 hours
  • Introduction to Fedora Electronic Lab - 0.5 hours
  • VLSI digital physical design theory - 1.5 hours

    • Afternoon session

  • Fedora Electronic Lab hands-on session - 2 hours
  • Entry to the talk will be based on the score of a screening test. The top 30 candidates will make it to the workshop
  • Registered participants will have to download the screening question set and send a soft copy of the answers in pdf format to arshadziyad@gmail.com before the deadline
  • Deadline is 7th of December 2009, 11PM
  • Decisions of the coordinators will be final and binding
  • Download screening question set by clicking here

    • Arshad Ziyad
    Ph: +91 80891 44465
    Email: arshadziyad@gmail.com

    Anusha S
    Ph: +91 +91 99952 38975
    Email: anushasubbu@gmail.com

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